Built for more than one day and not yet completed.
What should I pay attention to in this design?
Thanks.
Environment :
Xilinx ISE Design Suite Logic Edition, Version 14.7
VisualApplets Version 3.1
Jesse
Built for more than one day and not yet completed.
What should I pay attention to in this design?
Thanks.
Environment :
Xilinx ISE Design Suite Logic Edition, Version 14.7
VisualApplets Version 3.1
Jesse
Hi Jesse,
since the design you try to build is for a marathon card I would suggest you use Vivado instead of ISE. Vivado will greatly reduce your design times, since it has a better optimisation posibility than ISE.
As for your question what to do if there is only ISE(e.g. for a Ironman Card):
You can try to reduce parallelist of LUT and ROM operator to maximum 2(if you need more you can split them into multiple instanzes). This will result in a bit more resources, but it will reduce the clocking in this operators to only use the normal clock. Otherwise it will use a 2x faster clock as well which might make routing more complicated.
I hope that helps a bit.
Best regards,
Björn
Hi Roeger
I change the environment to Vivado version2018.2 and try it again.
The time of build has been shortened a lot.
Thank you very much.
Best regards,
Jesse
If possible, please use VIVADO, if applicable to your platform.
A detailed listing can be found in the VA 3 documentation:
Since you could build the applet now, we mark this thread as resolved now.