Posts by B.Ru

    Dear Silverfly,


    In the log I found:

    • PCIe Performance: PCIe is not highspeed capable
    • Currently trained PCIe speed: Gen 1 x4
    • ... payload size 128

    That at least indicates that 4 PCIe lanes are used, and a PCI payload size of 128.


    The facts above should deliver above 600 MB/s as DMA performance in your system.


    You can do a DMA performance test in mDisplay manually if you want to:

    1. Load a Acquisition Applet in mDisplay(X)
    2. Enable the simulator and the ROI at the expected target resolution
    3. Increase the frame rate step by step until you can see the buffer overflow and balance this to a working frane rate
    4. Resolution * Framerate * Pixeldepth = maximum target bandwiodth of DMA/PCIe

    Dear Saito-san,


    Thank you for this feedback. I forwarded your feedback to the product management.


    For now you can use the ParameterTranslation in order to rebuild certain details as far as possible with the aspect of making AcquisitionApplet's similar VA Designs.

    Dear Jayasuriya S.,


    Please check the DMA for the VA Design manually in microDisplay.

    So you have to build a CreateBlankImage approach instead of a camera into the design.

    Using SourceSelector would enable you to include the camera and the simulator at the same time.


    The CreateBlankImage operator would deliver as much data as the DMA can transfer.

    In microDisplay(X) you can see the obtained bandwidth and use this as a good indicator for the possible DMA performance.

    In case of further questions on this do not hesitate to contact me.

    Dear Silverfly,


    The amount of FPGA external RAM ressouces is currently restricted to a maximum of 4.

    In case of symmetric configurations and synchronization in between of the cameras an approach with InsertLine and AppendLine with ImageFIFOs directly behind the cameras it may become possible to write all camera image stream data into a single RAM ressource. That is additionally a question of the required bandwidth, because a single buffer needs to handle all 4 camera-streams at the same time.

    I have installed a Marathon VCL frame grabber with the runtime v5.6.1 and flashed my applet there. When I tried to do performance test in Micro diagnostics , I received an error attached here. Could anyone help on this?.

    forum.silicon.software/index.php?attachment/423/

    Please contact your local support center for issues like this.


    Basler Support contact list...


    From my point of view the not running perfromance test is not a real/hard issue as long as the hardware itself is present in microDiagnosis and microDisplay.

    It can be related to different version of applet in graber and existing file in runtime.

    Please let me know if our support could help you.


    Thank you.

    Dear rvdbijl,

    is the Ironman board limited to 4 DMA and 4 Imagebuffer instances? VA 3.2.0 won't let me add a 5th one in my project and pass Design Rules Level 1. The resource index won't go over 3 for either one

    The number fo DMA-Transfers is limited to 4. You can use InsertImage/AppendImage, InsertLine/AppendLine to show two images below of each other or next to each other using the Insert*/Appen* approach; please take care that these approaches require some synchronization memory for serializing lines or images. For two results/images that exist at the same time, please use InsertLine/AppendLine and a ImageFiFo (size 1 line per input) to handle the waiting time for the lines being forwarded one after the other. An image serialization is normally "cheaper" concerning hardware ressources that an additional DMA channel.

    The amount of ImageBuffers (real frame grabber hardware RAM modules) is limited to 4.

    Dear customer,


    Concerning your question. If you want to run mDisplay with a single camera and multiple DMAs,

    please make the following setting:

    mDisplay -> Tools -> Settings -> Check "Ignore Camclock status" and apply:

    304-pasted-from-clipboard-png


    That may help to start all DMA according to your requirements.


    If that is not showing the expected behaviour, then please paste your VA design here if possible.

    Thank you.

    Dear Theo,


    The Overflow parameter of the ImageBuffer operator is not stable enough to get a reliable feedback.

    That can not besolved by a parameter translation itself.


    This VA design OverFlowDetection_v01_BRudde.va will be a reliable approach:

    pasted-from-clipboard.png

    It measures the amount of pixels going into the FIFO and leaving it.

    By this the current fill-level can be seen while being the first memory behind the camera (infinite source = enabled) and directly in front of the first RAM related memory (inifinite source = disabled) operator.

    So in case the first RAM memory operator is not accepting or refusing the arriving data this can be detected.

    Additionally there is a EventToHost operator that sends an overflow event in case the small FIFO is geting filled up.

    A progressive detection on the basis of an OK, critical and error fill-level are used.

    Dear Pierre,


    I hope I understand or interpret your question correctly:

    The DMA transfer (DmaToPC's FG_FORMAT) mentions the wrong bitdepth?

    • 8 bit instead of 12?
    • Can you please check if the camera is sending 8/10/12 bit as expected?

    In case the camera sends 8 bit and the design expects 12, the representation of the data would look wrong for 12 bit visualization.

    Dear Theo,


    Thank you for this hint.

    I forwarded your input to the product and development management already.


    As far as I know is the naming of the runtime/SDK CXP Acq_QuadCXPx1* acquisition applets working with four single link cameras versus the VisualApplets operator with the name CXPQuadCamera sourced by two independent naming conventions.


    Both are using Quad, but the runtime applet name is supporting 4 cameras, while the VisualApplets (VA) operator is intended for 4 CXP links representing a single camera.


    Do you have a better naming for these CXP*Camera operators?

    Maybe: CXP6x1Camera, CXP6x2Camera, CXP6x4Camera


    Quote

    ...effect the parallelism I hope but it might, correct?

    The different VA CXP camera operators support parallelisms above the minimal one on its output node, which is based on maximum interface bandwidth and format mode setting (dynamic/static is affecting this). The paralleism in combination with the system clock defines the maximum bandwidth of a single link. When you selected the CXPQuadCamera operator you will have a default or parallelism 32. In case you require for your project CXPSingleCamera is will be 8.

    The current version of our CXPQuadCamera operator supports CXP x1 x2 x4 link configurations during runtime, and as words of solace I can tell you: The single(x1) or dual(x2) link CXP camera will work with the CXPQuadCamera (CXPx4) VA operator... 8o


    One more hint on something related to that:


    The minimal paralleism of the camera operator will always be used inside it and may affect the image resolution of the image going into your link with an optinally different paralleism.


    As an example for this:

    Camera delivers 1024 x 1024 pixels in a CXP6-4 configuration into the CXPQuadOperator.

    The operator is having a minimal paralleism of 20 and default of 32.


    So the image will get internally the line length of 1040 pixels. Then at the output it becomes a paralleism of 32 and this acts exactly like ParallelUP operator. So you get a line length of 1056 pixels into the link.

    Setting the maximum image width to the correct value is mandatory in this case.


    You can simply use ImageStatistics operator directly behind the camera operator to investigate this.

    After that a ImageBuffer will help selecting the real region of interest of the image.

    The paralleism is not affecting the image height directly.

    Ok, I am now completely of topic ... :huh:

    Hello,


    The remove image procedure inserts a delay of exactly one full frame.

    The previously inserted FIFO was able to store a single line.

    Because of that there was a deadlock as soon as the first line ran into the SYNC(module16)...


    Below you can see a screenshot of the solution and the VA source code below:

    pasted-from-clipboard.png


    Download VA Design: grab_test_BRudde_v01.va


    That version will work as expected.

    The VA simulation is not taking care of the synchronization in hardware,

    that detail needs to be fixed by the developer during design time.


    For explanation:

    The remove image approach causes a delay of a full frame in the upper link (by-pass) and requires a memory for a full frame.