The attached VA design is a simple example for color plane separation for RGB+IR intput and separated output. The example is made for CL-Medium 4 Tap 8 Bit cameras sending the data interleaved i.e. R + G + B + IR in the four taps. It works for the JAI Sweep+ series or RGBIR cameras on the Silicon Software mE5-MA-VCL FPGA frame grabber but can easily adapted to others.
The example uses the straight forward solution. There are many other options using a single DRAM operator for implementation only. The actual best solution depends on the requirements.