Posts by Jesse Lin

Hi there

I used the oscilloscope to get the waveform of the GPO output.

I found that the output waveform is different from the manual description.

About the test design please reference mE5MA_VCX-QP_IO_Test.va.

Environment

Platform : mE5MA VCX-QP (Front GPO)

Physical Properties of Trigger Signals Setting

00.PNG

Sample rate : 16 MHz

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Test 1

[Channel 0]

Process0/SelectSource_0/Select = 0

Source properties :

Downscale Downscale = 1

Downscale SelectedPulse = 1

signalWidth = 6250 tick * 8 ns (1/125 MHz) = 50 us

signalDelay= 1050 * 8 ns (1/125 MHz) = 8.4 us

[Channel 1]

Process0/SelectSource_1/Select = 2

Source properties :

Downscale Downscale = 2

Downscale SelectedPulse = 2

signalWidth = 5000 tick * 8 ns (1/125 MHz) = 40 us

signalDelay = 0 * 8 ns (1/125 MHz) = 0 us

Output

[Channel 0]

signal width = 62.25 us or 63.44 us

01.PNG

delay = 8.374 us

01-1.PNG

When set the Process0/ExSync/Exposure/Delay/delay = 0.

01-2.PNG

And I reference the Operator SignalDelay.

Delay Timing diagram .PNG

The delay signal should be negative. Why was the delay signal be positive?

And the signal width = 62.25 us or 63.44 us. Is this a phenomenon caused by physical circuits?

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Test 2

[Channel 0]

Process0/SelectSource_0/Select = 1

Source properties :

Downscale Downscale = 2

Downscale SelectedPulse = 1

signalWidth = 5000 tick * 8 ns (1/125 MHz) = 40 us

signalDdelay = 0 * 8ns (1/125MHz) = 0 us

[Channel 1]

Process0/SelectSource_1/Select = 2

Source properties :

Downscale Downscale = 2

Downscale SelectedPulse = 2

signalWidth = 5000 tick * 8 ns (1/125 MHz) = 40 us

signalDdelay = 0 * 8ns (1/125MHz) = 0 us

Output

02.PNG

And I reference the Operator Downscale

Downscale Timing diagram .PNG

Why did there appear pulses with a width about 6 us?

Thank you.

Jesse

Hi Bjoern

I have confirmed with camera manufacturers support this issue that was the camera sensor problem.

The camera is operating internally and will send one line in external edge mode.

Thank you for your reply.

Jesse

Hi Bjoern

Thanks for your suggest.

I will research in this direction.

Thank you.

Quote from Bjoern.Rudde

From my point of view both questions are something where the camera manual or the camera manufacturer support can give an answer. Is it possible to mention the camera name/manufacturer?

There is Camera Spec.[user's manual]

Jesse

Hi Bjoern

Quote from Bjoern.Rudde

Dear Jesse,

Please check with the VA design I posted above, if the line scan camera and the line trigger work as expected.

1. Configure the line scan camera for external trigger.
2. Send CXP trigger signals to the line scan camera.
3. Check if Amount of triggers matches the received number of lines.

If the line trigger works as expected, then we can go one step further.

Then we can use the ShaftEncoder direction and use this as a mask for the image trigger and/or transfer.

This is your design result [Test video].

1. Yes. It is external trigger mode.

2. In your design trigger signal is period.

3. TriggerMismatch.Status is jumping between of 9 and 10.

Jesse

In my application, some time encoder will be shock when the motion stops. So I used ShaftEncoderCompensate to offset the reverse pulse.

The goal is that camera(line scan) doesn't output line(image) when the motion stops.

In this design mE5MA_VCX-QP_Single_EncoderTest.va , the received lines counter still increase [Test video].

Why is there no trigger signal input but still received lines from the camera?

Thanks!

Jesse

Hi Pierre

Sorry about that I didn't describe the parameters of the camera clearly.

Camera setting :

Trigger mode : External edge [Camera spec P.37]

Scan Rate : 53.6 us

CameraParameter.PNG

Jesse

Hi there

I count the input signal and output image.

Please reference the designmE5MA_VCX-QP_Single_Capture.va and Test video

Why is there no trigger signal input at all, but the camera will always output images?

microDisplay setting:

Setting.PNG

Thank you

Jesse

Hi Bjoern

I compiled your design of mE5_MA_VCX-QP_Single_SplitImage_MOD_B.Rudde.va and ran it, but it could not work.

SplitImage.PNG

What parameters are I should pay attention to?

Thank you

Jesse

Hi Sir

I make a design to Split image even and odd lines into two images.

And I reference Bandwidth Bottlenecks to design.

But it has a deadlock, and I can not find the bug.

Simulation image [Link]

How to design without deadlock in this case?

Thank you

Jesse

Hi Björn,

Thank you so much for the help!

Jesse

Dear All.

I would assign encoder signal to flash two lights and I want to simulate signal.

How to generate the positive and negative signals of the encoder AB phase on Visual Applets?

Thanks.

Hi Johannes

Yes.CoefficientBuffer is no very easy to use with multiple output links.

Thank you very much.

Jesse

Hi Johannes

It is very clear explanation.

And I have a few doubt with mE5VQ8-CXP6D.

Are CoefficientBuffer's maximum memory size and bandwidth different with marathon?

Thank you.

Jesse

Hi Sir

I use 3 RAMs in VA design(mE5_MA_VCX-QP_Dual.va)

The platform microEnable 5 marathon(mE5_VCX-QP) has shared memory concept.

So these RAMs data width need more than 64*1(RMA1) + 8*8(RAM2) + 8*9(RAM3) = 200 bit.

Then increase parallelism to 32 before RAM1 and RAM2, and set ffc_factor parallelism to 4.

So these RAMs will share 256 bit. Then RAMs all have enough bandwidth. Is it right?

If move this design run on mE5VQ8-CXP6B. mE5VQ8-CXP6B doesn’t has shared memory concept.

The RAMs have independent data width. So I do not modify the parallelism to 32 and RAMs all have enough bandwidth?

This design use 96% LUT with mE5_MA_VCX-QP. It is possible to add applet in the future.

I try to reduce parallelism to 4, and modify board frequency to 250 MHz(mE5_MA_VCX-QP_Dual_250MHz.va). Compilation will fail(CmopileError.PNG).

If I want increase board frequency, Is there any detail in design that needs attention?

Thanks.

Jesse

Hi Johannes

I will send email to support@silicon-software.de.

Thank you.

Jesse

Hi Sir

When use GenICam Explorer to save parameters.[test video]

When use C# wrapper to save parameters.[test video]

Environment

Runtime: v5.6

Is there anything that needs to be set??

Thanks.

Jesse

Dear Bjorn

I try to modify ffc_factor (RAM) buffer height to 512 and load image height of 512.

Than Sync ffc_factor height to max.Now can dynamic modify image height!

But I need to try many times to get this result.It will take me a lot of time.Because it takes about an hour to build it once.

This is why I want to ask how to calculate about the design.

Jesse

Dear Bjorn

I try to reduce image height to 512 .

And change parameter from mE5_MA_VCX-QP_Single_Porj_AB_SpeedUp_BRudde.va

The output data is not synchronized. Test video[Link]

Is this design can dynamic reduce image height?[Height range : 512~1024]

The attachment is the final version in the project.

The line rate will up to 76923.

Thanks.

Jesse

Dear Bjorn

I am not quite sure about the structure of the shared memory concept.

Quote

You are using 3 RAM's modules on a marathon VCX-QP.

The memory bandwidth inside the VCX-QP is following a shared memory concept.

http://www.siliconsoftware.de/…t/device%20resources.html

The implemented RAM operators work at:

RAM Operator name	bit depth	parallelism (shared * 4)
RAM1	8	8 ( -> 32 )
RAM3	9	8 ( -> 32 )
ffc_factor	61	1 ( -> 4 )

Since all operators together share now:

64 / 72 / 64 bit

the design will not meet the expected performance.

Display More

In Shared Memory Concept

When a design utilizes all 4 RAM resources, each of the 4 RAM based operators can have up to 1.6 GB/s exclusive bandwidth, minus the efficiency factor of that particular operator.

So a RAM 's maximum bandwidth is 1.6 GB/s?

Why the design will not meet the expected performance?

Quote

What you need to do now:

Use parallelism of 32 for RAM1 and RAM3.

Use parallelism of 4 for ffc_factor.

Then the bandwidth would be handled correctly by the shared memory concept.

Since 3 RAMs need to share the same Pixel-rate in that design we use a factor of 4 for the parallelism to speed-up accordingly. A factor of 4 is not affecting the image dimension.

Display More

In Shared Memory Concept

Due to the shared bandwidth architecture, the applet developer should utilize all 256 bits of the operator’s memory interface (RAM Data Width) to achieve maximal throughput through the memory interface when using multiple RAM based operators even though the single RAM operator needs less bandwidth on its input.

mE5 marathon VCX-QP maximum RAM Data Width is 512 bits.

So set RAMs bandwidth to 256 bits?

Thank you.

Jesse

Porj_A(mE5_MA_VCX-QP_Single_proj_I) test video [Link]

Porj_B(mE5_MA_VCX-QP_Single_proj) test video [Link]

FFC_factor image [Link]

Porj_A can work at Line rate of 50000.

When I add HierarchicalBox of segment after HierarchicalBox of EdgexFilter (Porj_B).

Porj_B can not work at Line rate of 50000.

How can I calculate how many buffer need to add at Porj_B for Synchronization?

Thanks.

Jesse