Recent Activities

  • Ryo Saito

    Posted the thread Lossless encoding on FPGA.
    Thread
    Hello,

    Recently days, many customers are interested in saving all acquired images. Traceability is famous application but some customers want to save image for deep learning training.
    After saving image, there are two types way how to use images.
    1.…
  • Ryo Saito

    Replied to the thread Replacing HALCON operator.
    Post
    Dear Carmen-san,

    thank you very much for your swift answer.
    Yes, another solution is more better because we might be faced resource problem. Currently, this possibility information is enough for me. I will discuss more deeply with customer. Thank you.
  • CarmenZ

    Replied to the thread Replacing HALCON operator.
    Post
    Dear Saito-san,

    thank you for your question.
    I had a look on the description of Halcon function "fit_surface_first_order" (https://www.mvtec.com/doc/halc…_surface_first_order.html ) : This function approximates a first order surface plane to a gray…
  • Ryo Saito

    Posted the thread Replacing HALCON operator.
    Thread
    Dear Application team,

    I'd like to ask you possibility of replacement Halcon operator fit_surface_first_order by VisualApplets operators.
    https://www.mvtec.com/doc/halc…_surface_first_order.html

    Our customer inspect cable by Halcon but CPU load is…
  • Johannes Trein

    Like (Post)
    Dear Johannes-san,


    your sample looks working well. Thank you very much.

    Ryo Saito
  • Ryo Saito

    Post
    Dear Johannes-san,


    your sample looks working well. Thank you very much.

    Ryo Saito
  • CarmenZ

    Post
    Dear JSuriya,
    thank you for your request.
    Do you refer to the Visual Applets example "PrintInspection_Blob.va"?
    Please may you explain "reference points"? Do you mean rotation, translation and scaling with respect to a certain point (E.g center of…
  • Ryo Saito

    Post
    Dear Carmen-san,
    Dear Johannes-san,

    thank you very much for your advice. I will try to implement your idea in this week.
    After that, if I have question, please let me re-open this thread.

    Ryo Saito
  • JSuriya

    Post
    Dear CarmenZ,
    Is there possible to do Affine transformation (translation,rotation&scaling) with minimum 3 reference points in silicon software?


    Thanks&Regards,
    Jayasuriya
  • ArjunLucid

    Post
    Thanks for your suggestions Mr, Johannes Trein.
  • Johannes Trein

    Like (Post)
    I've made the C# example for new JPEG operator for Oliver, he has tested it and could go forward with his project. I'm attaching it here maybe it would be helpful for someone others.

    In the Zip file the .hap, .mcf and generated JEPG image are…
  • Hi JSuria

    let me add some ideas:
    - enable mDisplay -> Tools -> Settings -> Check "Ignore Camclock status"
    - disable mDisplay -> Tools -> Settings -> Check "Use GenICam Camera parameter"
    - start the acquisition in microDisplay FIRST
    - after start the…
  • Johannes Trein

    Post
    Dear Saito-san

    please see attached VA file which is used to output the average of a bouncy encoder and similar to the explanations given by Carmen described above.
    You need to add another DIV by 512 to get a 512 higher frequency.

    When I have time I…
  • Johannes Trein

    Post
    Hi Arjun

    Xilinx shows some system recommendations on their web pages like in https://www.xilinx.com/product…-tools/vivado/memory.html

    For mE5 marathon FPGAs Xilinx states that a maximum of 3GB RAM is used. For the future frame grabbers which are…
  • ArjunLucid

    Thread
    Hello,
    I would like to know the best CPU spec to run VA3 (along with Vivado in background) and get the designs compiled faster.
    1. Will it make any difference if we use intel or amd processor?
    2. Minimum number of CPU cores required?
    3. Minimum…
  • CarmenZ

    Post
    Dear Saito-san,
    thank you for your request.
    Maybe a combination of following operators is of interest for you:

    1. Signal Edge(Rising Edge):A pulse of one clock cycle is generated, when a rising edge of the input signal is detected
    2. SignalToWidth:The…
  • Ryo Saito

    Thread
    Dear All,

    I'd like to know your opinion.
    We want to make 512 times faster pulse on FPGA. Usually, ShaftEncoder module generate 4 times faster signal. If input encoder signal is 1kHz, I want to generate 512kHz signal. Do you have any idea of applet…
  • CarmenZ

    Post
    In the design "2020-2-27-LSTCA.va" you can furthermore save some FPGA resources: The SYNC operators in front of the division operations in modules "Lstca/aver" ,"Lstca/image2" and "Lstca/K2" are not necessary.
    Under
  • CarmenZ

    Post
    Dear Danna,
    thank you for your questions.

    1. Concerning you question from Februray 23rd:

    Please find attached the design "j_030320.va" : In this design an example for the calculation with so called fractional bits is implemented:
    For the calculation…
  • Dear CarmenZ,

    I have tried the attached applet 'MultipleProcesses' and still there is no image acquisition happening. I started image acquisiton one by one for each camera in Genicam explorer and set the 'trigger gate' parameter value to 1 for…