Hi Roeger
Thank you for your explanation.
Now I already know why this design needs to add buffer.
In the second project.
I will change the CXPSingleCamera to CXPDualCamera.The CXPDualCamera minimal parallelism is 12.So set the parallelism to 16 for test .And reduce the parallelism to 8 because lookuptable is not enough.This project has not been completed yet.
Now the amount of RAM is enough.
Remove the SYNC3 will appear warning.
And thank you for your suggestion.
Jesse
Hi Roeger
At #2
Yes. I want this design,but it can not work.
And I check level 1 with mE5_MA_VCX-QP_Get_Last_Row_BSR.va.
There is a error,please reference attachment (Error.PNG).
My visual applets version is 3.1.0.
At #3
When I use a "M" or "P" type applet with synchronization .
How can I calculate the buffer or FIFO size?
In this case, why LineBuffer need to add after module28?
Why the source image need add a RAM?
Before I post this thread.
I used guess to add RAM0.
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The applications I need are in the attachment.(mE5_VCX-QP_Single_Project_X.va)
When I flip a image with the synchronization ,it will use 1 or 2 RAM.
The board just has four RAM and I use five RAM in the process.
So I want to reduce the RAM ,when I flip a image with the synchronization.
Thanks.
Jesse
I need two images that are source and after filter.
To get the last row, source need to wait for a frame,so add a RAM on the source.
Have other way to get last row and fill it without RAM?
Thanks.
Hi Roeger
I change the environment to Vivado version2018.2 and try it again.
The time of build has been shortened a lot.
Thank you very much.
Best regards,
Jesse
Built for more than one day and not yet completed.
What should I pay attention to in this design?
Thanks.
Environment :
Xilinx ISE Design Suite Logic Edition, Version 14.7
VisualApplets Version 3.1
Jesse
