MA-VCL - Compilation Issue for 8K camera

  • Dear Support,

    We have created an Applet for capturing image from a 8k camera (Teledyne e2v Eliixa+ 8k monochrome) in full mode 8bitx8 tap. Image capturing at full resolution at 40KHz line rate is OK. But we also need a down-sampled image (width/2 and height/4) from another DMA. We used "Sample down" operator but it resulted in build error and some times it ran up to 12 hrs!. I also tried sampling down with other operators but that too not getting built/synthesized. Could you please guide me if there is any mistake in the design? Attaching the VA file for your reference. Refer "SampleDown" hierarchical block.

    Thanks,

    Arjun


    IRT_8K_V1.21.va

  • Dear Arjun Lucid,

    sorry for the late response. I built your design "IRT_8K_V1.21.va" using Vivado 2018. No problems occured and the overall processing time was 26 minutes.

    Which XilinX version and which VisualApplets version do you use?

  • free versions of Vivdo are available. I recommend to use a free version first.

    Under "http://www.siliconsoftware.de/download/live_docu/VA3/en/manuals/content/introduction.html"

    you can see an overview which XilinX versions are possible for which frame grabber.