Delay Train of pulses

  • Dear All,

    I need a sample VA program to delay a train of pulses using "Signal Delay" operator in "Multiple pulse" mode. I tried it, but it is not working as expected. So it would be good if some one can share a sample VA that works in following condition:

    Input pulse frequency --> 4 Hz

    Pulse delay - 10 seconds or in encoder pulses

    Board preferred --> me4 VD4 or VQ4

    Sample program attached for VQ4 --> Check in Process0/Trigger_Manipulator_Color/Delay



    Lucid Imaging Private Limited

  • Dear Arjun,

    Thank you for your question.

    The following design approach detects a signal at the external input and translates its rising edge into a single pulse.

    This single pulse is getting delayed in steps of one millisecond.

    Afterwards a new and fix duration is applied to it.

    In case of using the SignalDelay operator to directly applying the 10s delay it will use more than 11000% of the required FPGAs BlockRAM. By using a much lower clock at the input of SignalDelay it is possible with a minimum of ressources.


    VA Design as shown above:

    You can easily copy it to any VA platform.

  • Dear Arjun,

    The MultiPulse-Mode of the SignalDelay is of static character:

    the number of delay ticks is fixed after synthesis.

    SignalDelay in MultiPulse Mode will not reproduce the duration as expected in case the Tick input is downscaled.

    So it is recommended to use only the edge ( SignalEdge ) and apply the duration later.

    The possible/supported Delay duration itself is based on the Tick frequency applied.

    If using 10bit(can become more) for example, 1023 delay ticks are possible.

    Using 1000 pulses at tick input frequency 1 kHz will delay exactly 1 second.

    If you present finput = 4 Hz, the output frequency will be 4 Hz too, but delayed by the amount of ticks, where tick = ftick.

    finput can be delayed by the precision of ftick.

    So if you want to use different delays you can modify ftick during runtime instead of the SignalDelay delay parameter.

    ftick is normally generated by Generate operator.

    The pulse width in the sketch below is not valid in case of a tick frequency below system clock.

    So please only use the rising edge of the pulses and not as shown below:


  • B.Ru

    Closed the thread.