I use 3 RAMs in VA design(mE5_MA_VCX-QP_Dual.va)
|RAM Operator name||bit depth||parallelism|
The platform microEnable 5 marathon(mE5_VCX-QP) has shared memory concept.
So these RAMs data width need more than 64*1(RMA1) + 8*8(RAM2) + 8*9(RAM3) = 200 bit.
Then increase parallelism to 32 before RAM1 and RAM2, and set ffc_factor parallelism to 4.
So these RAMs will share 256 bit. Then RAMs all have enough bandwidth. Is it right?
If move this design run on mE5VQ8-CXP6B. mE5VQ8-CXP6B doesn’t has shared memory concept.
The RAMs have independent data width. So I do not modify the parallelism to 32 and RAMs all have enough bandwidth?
This design use 96% LUT with mE5_MA_VCX-QP. It is possible to add applet in the future.
I try to reduce parallelism to 4, and modify board frequency to 250 MHz(mE5_MA_VCX-QP_Dual_250MHz.va). Compilation will fail(CmopileError.PNG).
If I want increase board frequency, Is there any detail in design that needs attention?