The Silicon Software AcquisitionApplets have a build in trigger sequencer and queue.
If trigger inputs exceed the minimum allowed output period, pulses are queued and delayed. This will kill the timing but will keep the trigger synchronized. The example is made for a Silicon Software mE5-MA-VCL frame grabber but can be easily adapted to any other FPGA frame grabber.
The attached example has the following functions:
- external trigger input or software trigger
- trigger pulse multiplication 1:N
- trigger queue
- trigger output period limitation
- exsync output
The implementation was tested with a logic analyzer. The following screenshot shows an input period of 5ms. The applet is configured to a multiplication of 2 pulses with a minimum output period of 2.5ms.
If we increase the input period, the output will be delayed and the queue will be filled with pulses.
If the gap between input pulses gets sufficiently large enough, the queue will compensate it. In the example 5 input pulses with a period of 2.9ms will generate 10 output pulses with a period of 2500 ms.
NOTE: This example is not trigger scaling
If you want to scale an input trigger e.g. an encoder signal by a multiplication and division factor you need to measure the input period, scale it and generate pulses. This is not the purpose of this example.